Semiconductor device and method of anodization for the semiconductor device

ABSTRACT

A first p-type silicon layer ( 3 ) is formed as a buried layer in a p-type single crystal silicon substrate ( 2 ), and an n-type silicon layer ( 4 ) is formed on the upper side of the silicon substrate ( 2 ). A second p-type silicon layer ( 5 ) for forming an opening is defined in the n-type silicon layer ( 4 ), and a metal protecting film ( 14 ) is formed on the upper side of the n-type silicon layer ( 4 ). An electrode layer ( 18 ) is formed on the rear side of the silicon substrate ( 2 ) via an oxide film (17). The electrode layer ( 18 ) and the silicon substrate ( 2 ) are electrically connected to each other via a connecting opening ( 17   a ) at portions aligned with the first p-type silicon layer ( 3 ). After a positive terminal and a negative terminal of a DC power source (V) are connected to the electrode layer ( 18 ) and to a counter electrode ( 11 ) respectively, a voltage is applied between the electrode layer ( 18 ) and the counter electrode ( 11 ) to carry out anodization.

BACKGROUND OF THE INVENTION

The present invention relates generally to a semiconductor device and ananodization process for the same, and more particularly to ananodization process for imparting porosity to semiconductor devices atdesired sites.

Anodization of silicon substrates has conventionally been practiced inmicro-machining of silicon. An example of the conventional anodizationprocess will now be described.

FIG. 5 shows a silicon substrate to be employed in a semiconductordevice or acceleration sensor. In this drawing, a p-type silicon layer 3is formed on the front side of a plane-oriented (110) p-type singlecrystal silicon substrate (hereinafter referred simply to as siliconsubstrate) 2 over a predetermined area. The p-type silicon layer 3 has ahigher silicon concentration than the silicon substrate 2, and anepitaxial growth layer 4 of n-type single crystal silicon is formed overthe upper surface of the silicon substrate 2. The p-type silicon layer 3is buried under the epitaxial growth layer 4. A p-type silicon layer 5for forming an opening 15 is defined in the epitaxial growth layer 4,and the layer 5 extends from the surface of the epitaxial growth layer 4to the p-type silicon layer 3. On the epitaxial growth layer 4 excludingthe area where the p-type silicon layer 5 is formed, an oxide (SiO₂)film 6 as a layer insulating film, a wiring pattern 7 such as ofaluminum, a SiN or Si₃N₄ passivation film 8 for insulating the surfacelayer, and a resin protecting film 9 such as of photoresist having HFresistance are formed.

As shown in FIG. 6, the silicon substrate 2 is immersed together withthe layers 3 to 9 in an aqueous HF solution (aqueous hydrofluoricsolution) 10, and a counter electrode 11 which is a noble metal platesuch as of Pt is disposed opposing the silicon substrate 2. An anode ofa DC power source V is connected to the silicon substrate 2, and itscathode is connected to the counter substrate 11. Anodization is carriedout by application of an electric field between the substrate 2 and thecounter electrode 11. The p-type silicon layers 3 and 5 are converted toporous silicon layers, and the porous portions thus formed are removedby alkali etching in a later step to form a cavity. The epitaxial growthlayer (n-type single crystal silicon) 4 present above the cavityconstitutes a hollow beam and also assumes the structure of anacceleration sensor.

However, there are problems in that currents from the DC power source Vin the anodization treatment diffuse to areas which need not beanodized, as indicated by the arrows in FIG. 5. This diffusion ofelectric currents (reactive currents) causes a voltage drop, whichlowers the anodization rate in the areas to be anodized and the rangesto be subjected to porosity imparting treatment spread to the siliconsubstrate 2 side beyond the desired areas (i.e., p-type silicon layers 3and 5). Accordingly, a cavity is formed beyond the desired area by thealkali etching in the later step.

It is an objective of the present invention to provide a process foranodizing a silicon substrate which can efficiently impart porosityselectively to the silicon substrate.

SUMMARY OF THE INVENTION

In order to attain the above objective, in the anodization processaccording to the present invention, the semiconductor device has ap-type single crystal silicon substrate. A first p-type silicon layer isformed on a first side of the p-type single crystal silicon substrateover a predetermined area. An n-type silicon layer is formed on thefirst side of the p-type single crystal silicon substrate. The firstp-type silicon layer is a buried layer located under the n-type siliconlayer. A second p-type silicon layer is defined in the n-type siliconlayer so as to form an opening. A protecting film is formed on then-type silicon layer with the surface of the second p-type silicon layerbeing exposed. An insulating film is formed on a second side, other side(the side opposite to the first side) of the p-type single crystalsilicon substrate. An electrode layer which is formed under theinsulating film has a connecting section at a portion aligned with thefirst p-type silicon layer and is connected electrically via theconnecting section to the p-type single crystal silicon substrate. Theanodization process includes the step of connecting a positive terminalof a DC power source to the electrode layer and also connecting itsnegative terminal to a counter electrode disposed to oppose the p-typesingle crystal silicon substrate and the step of applying a voltagebetween the electrode layer and the counter electrode so as to impartporosity to the first and second p-type silicon layers.

In the present invention, since the electrode layer is brought intocontact with the p-type single crystal silicon substrate via theconnecting section at least at the portion aligned with the buriedp-type silicon layer, electric currents concentrate, when anodization iscarried out, in the p-type silicon layer zone. Meanwhile, reactivecurrents diffusing to portions which are not to be anodized areinhibited. Thus, porosity is imparted selectively to the desiredportions (selective porosity imparting treatment).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view showing a silicon substrate;

FIG. 2 is a schematic cross-sectional view showing a process foranodizing the silicon substrate shown in FIG. 1;

FIG. 3 is a schematic cross-sectional view showing a silicon substrateaccording to another embodiment;

FIG. 4 is a schematic cross-sectional view showing a silicon substrateaccording to still another embodiment;

FIG. 5 is a schematic cross-sectional view showing a silicon substrateof the prior art; and

FIG. 6 is a schematic cross-sectional view showing a process foranodizing the silicon substrate shown in FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT First Embodiment

The anodization process according to a first embodiment of the presentinvention will be described below referring to FIGS. 1 and 2.

It should be noted that in the following embodiments, including thefirst embodiment, the same or like components are affixed with the samereference numbers as in the prior art respectively, and a detaileddescription of such elements will be omitted. Film and layers shown inthe drawings including FIG. 1 are enlarged for convenience, and theirthicknesses are not shown proportional to actual thicknesses.

In this embodiment, a thin metal protecting film (hereinafter simplyreferred to as metal protecting film) 14 is formed in place of the resinprotecting film 9 on the passivation film 8. This metal protecting film14 is formed to cover the entire surface of the silicon substrate 2including the upper surface of the passivation film 8 by means of aphysical film forming method such as W (tungsten) sputtering and vacuumvapor deposition. The metal protecting film 14 may be formed usingmolybdenum.

W silicide 20 having a thickness of about 1 μm is formed along theinterface between the metal protecting film 14 and the epitaxial growthlayer 4 of the silicon substrate 2 over the area immediately below theopening of the passivation film 8. The W (tungsten) comprising the metalprotecting film 14 and the W silicide 20 have an HF resistance. Afterformation of the metal protecting film 14 over the entire surface of thesilicon substrate 2, an opening 15 is formed in it by means ofphotolithography and etching at the portion aligned with the p-typesilicon layer 5, as shown in FIG. 1.

A p-type silicon layer 16 is formed by doping using boron as an impurityby means of ion implantation to the silicon substrate 2 on the lowerside and heat-diffusing the implanted boron. This p-type silicon layer16 corresponds to the p-type impurity-diffused area of the presentinvention and has an electrical resistance which is lower than that ofthe silicon substrate 2.

An oxide film (SiO₂) 17 is formed as an insulating film by means ofpatterning on the lower surface of the p-type silicon layer 16, andfurther an electrode layer 18 which is an aluminum thin film is formedby means of physical film forming methods including sputtering andvacuum vapor deposition. The oxide film 17 may be replaced with otherinsulating films such as of SiN. In the oxide film 17, a connectingopening 17 a is formed in alignment with the buried p-type silicon layer3 and the p-type silicon layer 5. The electrode layer 18 and the p-typesilicon layer 16 are electrically connected to each other via theconnecting opening 17 a. The electrode layer 18 is electricallyconnected to the p-type silicon substrate 2 via the p-type silicon layer16.

Next, the silicon substrate 2 is immersed in an aqueous HF solution 10,as shown in FIG. 2. The electrode layer 18 is connected to the positiveterminal of a DC power source V, and the negative terminal of the DCpower source is connected to the counter electrode 11, and then anelectric field is applied between the electrodes to effect anodization.

By this anodization treatment, the p-type silicon layers 3 and 5 areconverted to porous silicone layers. In this anodization treatment,porosity is imparted selectively to the areas to be anodized, i.e. thep-type silicon layers 3 and 5 which are the areas to be anodized.

Subsequently, the thus formed porous portions are subjected toanisotropic etching by means of alkali etching using TMAH (tetramethylammonium hydroxide). In this treatment, the p-type silicon layers 3 and5 having undergone the anodization treatment and then the porosityimparting treatment are readily soluble in alkali.

A cavity (not shown) is formed by removing the porous silicon layer bythis alkali etching. Thus, the epitaxial growth layer (n-type singlecrystal silicon) 4 located above the cavity is allowed to constitute ahollow beam and assume an acceleration sensor structure in thisembodiment.

The process of the present invention exhibits the following effects.

(1) According to the anodization process of this embodiment, sinceelectric currents flow through the connecting opening 17 a from theelectrode layer 18 without diffusion, as indicated by the arrows in FIG.1, the density of the currents flowing into the p-type silicon layers 3and 5 is increased. Consequently, the rate of anodization for convertingthe p-type silicon layers 3 and 5 to porous silicon layers is increasedcompared with the prior art. Further, the occurrence of no diffusion ofelectric currents increases the density of the electric currents flowinginto the p-type silicon layers 3 and 5. That is, porosity can beimparted selectively to the p-type silicon layers 3 and 5, since theflow of electric currents concentrate to them.

(2) The p-type silicon layer 16 having an electrical resistance lowerthan that of the silicon substrate 2 provided on the lower side of thesilicon substrate 2 can reduce contact resistance between the electrodelayer 18 and the silicon substrate 2. Even if the anodization treatmentis carried out in the absence of this p-type silicon layer 16, the aboveeffect (1) can be exhibited. However, porosity can be more efficientlyimparted selectively to the p-type silicon layers 3 and 5, since thelow-resistance p-type silicon layer 16 causes electric currents toconcentrate to the layers 3 and 5.

(3) The W (tungsten) metal protecting film 14 has a high melting pointand also has a coefficient of heat expansion approximate to those of theSiN or Si₃N₄ passivation film 8 and of the epitaxial growth layer 4 andadheres with them, causing no separation of the metal protecting film14.

(4) The portions covered with the metal protecting film 14 are protectedby it from attack of the aqueous HF solution. Further, the W silicide 20present between the metal protecting film 14 and the epitaxial growthlayer 4 prevents the aqueous HF solution from intruding into the inside.

Second Embodiment

Next, the anodization process according to a second embodiment of thepresent invention will be described referring to FIG. 2. The differencebetween this embodiment and the first embodiment is that the anodizationtreatment is carried out with the negative terminal of the DC powersource being connected not to the counter electrode 11, but to the metalprotecting film 14, as indicated by the two-dot chain line shown in FIG.2.

The anodization process according to the second embodiment exhibits thefollowing merits:

In the conventional anodizing treatment, as shown in FIG. 6, the surfacearea of the counter electrode 11 should be the same as that of thesilicon substrate 2 so as to carry out uniform anodization. Meanwhile,according to the anodization process of this embodiment, since the metalprotecting film 14 is used as the counter electrode, there is no need touse a noble metal plate as the counter electrode 11. Accordingly, theanodization treatment can be carried out inexpensively compared with theprior art. Further, since the metal protecting film 14 is formed overalmost all over of surface of the silicon substrate 2, anodization canbe carried out uniformly.

Furthermore, since the metal protecting film 14 is formed adjacent tothe silicon substrate 2 and is used as the counter electrode, there isno need to consider the electrical resistance of the aqueous HF solution10. In other words, in the case where the silicon substrate and thecounter electrode are spaced from each other, the anodization treatmentshould be carried out under control of the electric current or voltageof the DC power source V considering the electrical resistance of theaqueous HF solution 10. In this embodiment, however, there is no need toconsider the resistance of the aqueous HF solution 10, so that theanodization treatment can be more readily facilitated.

Third Embodiment

The anodization process according to a third embodiment of the presentinvention will be described referring to FIG. 3. It should beappreciated that in the following embodiments including the thirdembodiment the anodization treatment is carried out by immersing thesilicon substrate 2 into the aqueous HF solution.

In this embodiment, a p-type silicon area 16 a is formed in place of thep-type silicon layer 16 used in the first embodiment. This p-typesilicon area 16 a is formed by doping using boron as an impurity, forexample, by means of ion implantation into the lower side of the siliconsubstrate 2 via the opening 17 a formed by patterning the oxide film 17and heat-diffusing the thus implanted boron. This p-type silicon area 16a corresponds to the p-type impurity-diffused area and has an electricalresistance lower than that of the p-type silicon layer 16 in the firstembodiment.

Since this p-type silicon area 16 a reduces the contact resistancebetween the electrode layer 18 and the silicon substrate 2, the densityof electric currents flowing through the p-type silicon layers 3 and 5during the anodization treatment is further increased.

Fourth Embodiment

Next, the anodization process according to a fourth embodiment of thepresent invention will be described referring to FIG. 4. As shown inFIG. 4, in this embodiment, two n-type single crystal silicon epitaxialgrowth layers 4A and 4B are built up on the upper side of the siliconsubstrate 2, and two p-type silicon layers 3A and 3B are formed asburied layers in the epitaxial growth layers 4A and 4B, respectively.The p-type silicon layers 3A and 3B contain higher concentrations ofboron as the impurity than the silicon substrate 2. The p-type siliconlayers 3A and 3B are diffused as far as into the silicon substrate 2 andthe epitaxial growth layer 4A located below them, respectively. Thep-type silicon layers 3A and 3B are brought into contact with eachother, and the p-type silicon layer 3A located on the lower side isarranged to oppose the connecting opening 17 a. A p-type silicone area16 a is formed on the silicon substrate 2 at the portion aligned withthe connecting opening 17 a.

Meanwhile, a pair of p-type silicon layers 5 for forming openings 15 aredefined in the epitaxial growth layer 4B, spaced from each other. Thep-type silicon layers 5 extend from the upper face of the epitaxialgrowth layer 4B to the p-type silicon layer 3B.

The above silicon substrate 2 is subjected to anodization in the samemanner as in the first or second embodiment using the counter electrode11 or the metal protecting film 14 as the counter electrode.

The p-type silicon layers 3A, 3B and 5 are converted to porous siliconlayers by this anodization treatment. The contact resistance between theelectrode layer 18 and the silicon substrate 2 is lowered by the p-typesilicon area 16 a in this anodization treatment, so that electriccurrents flow through the connecting opening 17 a from the electrodelayer 18 with no diffusion as indicated by the arrows shown in FIG. 4.Accordingly, the density of electric currents flowing into the p-typesilicon layers 3A, 3B and 5 is increased, and the rate of anodizationfor converting the p-type silicon layers 3A, 3B and 5 into poroussilicon layers is increased compared with the prior art. Further, sinceno diffusion of electric currents occurs, the electric currents areconcentrated in the p-type silicon layers 3A, 3B and 5, which are areasto be anodized, and thus porosity can efficiently be imparted to theselayers selectively.

Accordingly, the epitaxial growth layer 4B shown at the center of thedrawing assumes a hollow structure, when the porous portions are removedby etching.

The embodiments of the present invention may be modified as follows:

(1) The plane-oriented (110) p-type single crystal silicon substrate 2may be replaced with substrates having other plane orientations (111)and (100).

(2) An alkaline etchant such as KOH, hydrazine, or EPW(ethylenediamine-pyrocatechol-water) may be used in place of TMAH.

(3) The p-type silicon layer 16 in the first embodiment may be omitted.Further, the p-type silicon areas 16 a in the third and fourthembodiments may be omitted.

It should be noted here that anodization referred to in thisspecification is defined to be a series of modification treatments forforming porous layers in a substrate by applying electric currents in anelectrolyte to the substrate serving as an anode.

What is claimed is:
 1. A process for anodizing a semiconductor devicecontaining a p-type single crystal silicon substrate, the semiconductordevice comprising: a first p-type silicon layer formed on a first sideof the substrate over a predetermined area; an n-type silicon layerformed on the first side of the substrate, the first p-type siliconlayer being buried under the n-type silicon layer; a second p-typesilicon layer for forming an opening defined in the n-type siliconlayer; a protecting film formed on the n-type silicon layer with thesurface of the second p-type silicon layer being exposed; a silicideformed between the protecting film and the n-type silicon layer, whereinthe protecting film and the silicide are formed of metals having a highHF resistance; an insulating film formed on a second side opposing thefirst side of the substrate; and an electrode layer formed on theinsulating film, which has a connecting section formed at a portionaligned with the first p-type silicon layer, and connected electricallyvia the connecting section to the substrate; the process comprising thesteps of: connecting respectively a positive terminal and a negativeterminal of a DC power source to the electrode layer and to a counterelectrode disposed to oppose the substrate; and applying a voltagebetween the electrode layer and the counter electrode in an HF solutionso as to impart porosity to the first and second p-type silicon layers.2. The process for anodizing a semiconductor device according to claim1, wherein the semiconductor device further comprises a p-typeimpurity-diffused area formed on the second side of the substrate and incontact with the connecting section.
 3. The process for anodizing asemiconductor device according to claim 1, wherein the counter electrodeis a protecting film made from a thin metal film.
 4. The process foranodizing a semiconductor device according to claim 1, wherein theprotecting film is formed either of tungsten or molybdenum.
 5. Theprocess for anodizing a semiconductor device according to claim 1,further comprising the step of applying electric currents in order toconcentrate to the p-type silicon layer without diffusion.
 6. Theprocess for anodizing a semiconductor device according to claim 2,wherein the semiconductor device has a pair of the second p-type siliconlayers, and the protecting film has a pair of openings at portionsaligned with the second p-type silicon layers, respectively.